Location:
Search - USB2.0 VHDL
Search list
Description: USB2.0的VHDL描述，很经典了，欢迎大家下载
Platform: |
Size: 61085 |
Author: 张亮 |
Hits:
Description: usb2.0的vhdl源码,具有详细的说明文档.
Platform: |
Size: 197420 |
Author: zjc |
Hits:
Description: FPGA实现USB2 原理-FPGA USB2 Principle
Platform: |
Size: 113664 |
Author: 陈平 |
Hits:
Description: USB2.0的VHDL描述，很经典了，欢迎大家下载-USB2.0 the VHDL description, very classic, and welcomes everyone to download
Platform: |
Size: 61440 |
Author: 张亮 |
Hits:
Description: usb2.0的vhdl源码,具有详细的说明文档.-USB2.0 the VHDL source code, with detailed documentation.
Platform: |
Size: 197632 |
Author: zjc |
Hits:
Description: USB 通用串行总线技术规范简介,这个是中文的.找了好久啊!-USB Universal Serial Bus specification Introduction, is that this is in Chinese. Looking for a long time ah!
Platform: |
Size: 40960 |
Author: Liziler |
Hits:
Description: usb2.0 ip 文挡齐全,并已经过FPGA的验证,希望大家支持-usb2.0 ip complete text block, and has been FPGA verification, I hope you will support
Platform: |
Size: 208896 |
Author: kin |
Hits:
Description: VHDL USB2.0接口源码,内有说明,详细.-VHDL USB2.0 interface source code, which is described in detail.
Platform: |
Size: 196608 |
Author: dushibiao |
Hits:
Description: 基于FPGA的USB2.0的实现方法，适用于急需开发usb2.0的人员-FPGA-based on the realization of USB2.0 method, applied to the urgent need to develop personnel USB2.0
Platform: |
Size: 113664 |
Author: fiann |
Hits:
Description: usb cy7c68013开发板中CPLD的源代码-USB2.0-128P to restore the I2C settings dev_io
Platform: |
Size: 2048 |
Author: 桂霖 |
Hits:
Description: Actel 的高速USB接口下载版电路原理图。USB2.0+FPGA。想做个所USB接口通信的可以参考。-Actel IGLOO_Icicle scematics.
Platform: |
Size: 47104 |
Author: ali |
Hits:
Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码,包括文档-Complete Verilog language developed by USB2.0 IP core source code, including documentation
Platform: |
Size: 206848 |
Author: 陈润 |
Hits:
Description: High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support.
For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled
in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB
signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0
signaling running at hundreds of MHz, the existing design methodology must change.
Platform: |
Size: 342016 |
Author: rex |
Hits:
Description: UTMI全称为 USB2.0 Transceiver Macrocell Interface，此协议是针对USB2.0的信号特点进行定义的，分为8位或16位数据接口。目的是为了减少开发商的工作量，缩短产品的设计周期，降低风险。此接口模块主要是处理物理底层的USB协议及信号，可与SIE整合设计成一专用ASIC芯片，也可独立作为PHY的收发器芯片，下以8位接口为例介绍PHY的工作原理及设计特点。
-UTMI called USB2.0 Transceiver Macrocell Interface, this agreement is a signal for USB2.0-defined characteristics, is divided into 8-bit or 16-bit data interface. The purpose is to reduce the workload of developers to shorten product design cycles, reduce risk. This interface module is mainly to deal with the underlying physics of the USB protocol and signaling, can be integrated with the SIE designed a dedicated ASIC chips, can also be independent of the transceiver as a PHY chip, the next eight to PHY interface as an example to introduce the working principle and design features.
Platform: |
Size: 210944 |
Author: leixueyan |
Hits:
Description: 实现USB2.0接口控制的VHDL源代码-USB2.0 VHDL code
Platform: |
Size: 196608 |
Author: sky |
Hits:
Description: 通用接口usb2.0的verilog开发代码-Common interface usb2.0 development of the verilog code
Platform: |
Size: 205824 |
Author: wx |
Hits:
Description: usb2.0 transceiver macrocell interface(UTMI) 1.05版本-usb2.0 transceiver macrocell interface (UTMI) 1.05 version of the
Platform: |
Size: 338944 |
Author: |
Hits:
Description: usb2.0 fpga程序 用vhdl语言编写 quartus环境实现
-usb2.0 fpga using vhdl language program quartus environment to achieve
Platform: |
Size: 3567616 |
Author: PETER |
Hits:
Description: USB2.0 IP核,ASIC,FPGA可用,Verilog HDL源代码-USB2.0 IP,Verilog HDL
Platform: |
Size: 64512 |
Author: AmazingEric |
Hits:
Description: vhdl for usb2.0 interface-vhdl for usb2.0
Platform: |
Size: 3072 |
Author: gerile |
Hits: